The increasing demand for performance and features in a broad array of computing devices has led manufactures to include multiple central processor units (CPUs) in computing devices to handle a greater number of capabilities and heavier workloads while executing faster than previous generations. Some architectures include CPUs arranged into clusters for executing different tasks and supporting different capabilities. A computing device may include a multi-cluster CPU system to handle the demands of the software and subsystems of the computing device. The number of CPUs can only advance the performance of the computing device if the CPUs can access stored code and data with speeds comparable to their processing speed. Too many CPUs requesting access to a cache memory can cause a performance bottleneck.
To avoid creating this performance bottleneck, each CPU cluster may include its own cache memory, for example an L2 cache. In many instances, not all of the CPU clusters of a computing device may be active, or the cache of a CPU cluster may not be fully utilized. Existing cache coherency protocols support sharing of data among L2 caches of different CPU clusters. However, these cache coherency protocols fail to fully exploit the available L2 cache resources in the multi-cluster CPU system. The preferred L2 cache to be leveraged for supporting other active CPU clusters would be the L2 cache of the multi-cluster CPU system having both the lowest latency and the highest availability. This preferred circumstance is not always present when looking to leverage other L2 cache resources for a CPU cluster. Further, even combining the highest availability and lowest latency may not provide the combination with the best performance results.